---
 gcc-3.4.4/gcc/config/arm/arm.md |  144 ----------------------------------------
 1 files changed, 144 deletions(-)

Index: b/gcc-3.4.4/gcc/config/arm/arm.md
===================================================================
--- a/gcc-3.4.4/gcc/config/arm/arm.md
+++ b/gcc-3.4.4/gcc/config/arm/arm.md
@@ -1744,150 +1744,6 @@
    }"
 )
   
-;;; ??? This pattern is bogus.  If operand3 has bits outside the range
-;;; represented by the bitfield, then this will produce incorrect results.
-;;; Somewhere, the value needs to be truncated.  On targets like the m68k,
-;;; which have a real bit-field insert instruction, the truncation happens
-;;; in the bit-field insert instruction itself.  Since arm does not have a
-;;; bit-field insert instruction, we would have to emit code here to truncate
-;;; the value before we insert.  This loses some of the advantage of having
-;;; this insv pattern, so this pattern needs to be reevalutated.
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "")
-                         (match_operand:SI 1 "general_operand" "")
-                         (match_operand:SI 2 "general_operand" ""))
-        (match_operand:SI 3 "reg_or_int_operand" ""))]
-  "TARGET_ARM"
-  "
-  {
-    int start_bit = INTVAL (operands[2]);
-    int width = INTVAL (operands[1]);
-    HOST_WIDE_INT mask = (((HOST_WIDE_INT)1) << width) - 1;
-    rtx target, subtarget;
-
-    target = operands[0];
-    /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical 
-       subreg as the final target.  */
-    if (GET_CODE (target) == SUBREG)
-      {
-	subtarget = gen_reg_rtx (SImode);
-	if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target)))
-	    < GET_MODE_SIZE (SImode))
-	  target = SUBREG_REG (target);
-      }
-    else
-      subtarget = target;    
-
-    if (GET_CODE (operands[3]) == CONST_INT)
-      {
-	/* Since we are inserting a known constant, we may be able to
-	   reduce the number of bits that we have to clear so that
-	   the mask becomes simple.  */
-	/* ??? This code does not check to see if the new mask is actually
-	   simpler.  It may not be.  */
-	rtx op1 = gen_reg_rtx (SImode);
-	/* ??? Truncate operand3 to fit in the bitfield.  See comment before
-	   start of this pattern.  */
-	HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
-	HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
-
-	emit_insn (gen_andsi3 (op1, operands[0], GEN_INT (~mask2)));
-	emit_insn (gen_iorsi3 (subtarget, op1,
-			       gen_int_mode (op3_value << start_bit, SImode)));
-      }
-    else if (start_bit == 0
-	     && !(const_ok_for_arm (mask)
-		  || const_ok_for_arm (~mask)))
-      {
-	/* A Trick, since we are setting the bottom bits in the word,
-	   we can shift operand[3] up, operand[0] down, OR them together
-	   and rotate the result back again.  This takes 3 insns, and
-	   the third might be mergeable into another op.  */
-	/* The shift up copes with the possibility that operand[3] is
-           wider than the bitfield.  */
-	rtx op0 = gen_reg_rtx (SImode);
-	rtx op1 = gen_reg_rtx (SImode);
-
-	emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
-	emit_insn (gen_lshrsi3 (op1, operands[0], operands[1]));
-	emit_insn (gen_iorsi3  (op1, op1, op0));
-	emit_insn (gen_rotlsi3 (subtarget, op1, operands[1]));
-      }
-    else if ((width + start_bit == 32)
-	     && !(const_ok_for_arm (mask)
-		  || const_ok_for_arm (~mask)))
-      {
-	/* Similar trick, but slightly less efficient.  */
-
-	rtx op0 = gen_reg_rtx (SImode);
-	rtx op1 = gen_reg_rtx (SImode);
-
-	emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
-	emit_insn (gen_ashlsi3 (op1, operands[0], operands[1]));
-	emit_insn (gen_lshrsi3 (op1, op1, operands[1]));
-	emit_insn (gen_iorsi3 (subtarget, op1, op0));
-      }
-    else
-      {
-	rtx op0 = GEN_INT (mask);
-	rtx op1 = gen_reg_rtx (SImode);
-	rtx op2 = gen_reg_rtx (SImode);
-
-	if (!(const_ok_for_arm (mask) || const_ok_for_arm (~mask)))
-	  {
-	    rtx tmp = gen_reg_rtx (SImode);
-
-	    emit_insn (gen_movsi (tmp, op0));
-	    op0 = tmp;
-	  }
-
-	/* Mask out any bits in operand[3] that are not needed.  */
-	   emit_insn (gen_andsi3 (op1, operands[3], op0));
-
-	if (GET_CODE (op0) == CONST_INT
-	    && (const_ok_for_arm (mask << start_bit)
-		|| const_ok_for_arm (~(mask << start_bit))))
-	  {
-	    op0 = GEN_INT (~(mask << start_bit));
-	    emit_insn (gen_andsi3 (op2, operands[0], op0));
-	  }
-	else
-	  {
-	    if (GET_CODE (op0) == CONST_INT)
-	      {
-		rtx tmp = gen_reg_rtx (SImode);
-
-		emit_insn (gen_movsi (tmp, op0));
-		op0 = tmp;
-	      }
-
-	    if (start_bit != 0)
-	      emit_insn (gen_ashlsi3 (op0, op0, operands[2]));
-	    
-	    emit_insn (gen_andsi_notsi_si (op2, operands[0], op0));
-	  }
-
-	if (start_bit != 0)
-          emit_insn (gen_ashlsi3 (op1, op1, operands[2]));
-
-	emit_insn (gen_iorsi3 (subtarget, op1, op2));
-      }
-
-    if (subtarget != target)
-      {
-	/* If TARGET is still a SUBREG, then it must be wider than a word,
-	   so we must be careful only to set the subword we were asked to.  */
-	if (GET_CODE (target) == SUBREG)
-	  emit_move_insn (target, subtarget);
-	else
-	  emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget));
-      }
-
-    DONE;
-  }"
-)
-
 ; constants for op 2 will never be given to these patterns.
 (define_insn_and_split "*anddi_notdi_di"
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")